Electrical and Electronics Engineering Institute

University of the Philippines - Diliman

Louis Alarcon

Position: 
Assistant Professor
Laboratory Affiliation: 
Intel Microprocessors Laboratory
Room: 
409
Telephone Number: 
+63 2 981 8500 local 3380
Educational Background: 
PhD in Electrical Engineering and Computer Science University of California Berkeley, 2010
Research Interest/Activities: 

I am the current head of the UP EEEI Microelectronics Laboratory (www.up-microlab.org), and we are currently working on developing next generation sensor networks, covering key technologies, including (1) low energy and low voltage integrated circuit (IC) design, (2) integrated and discrete energy harvesting for resilient, large-scale, and zero-maintenance sensor nodes and networks, and (3) scalable and intelligent frameworks for distributed sensor and network data processing.

I am supervising the following projects: (1) The SmartWire Project, funded by DOST-PCIEERD, (2) The RESE2NSE Project, in collaboration with UC Berkeley, and funded by CHED-PCARI. In addition to government funding, the Microelectronics Laboratory is also supported by our industry partner, Analog Devices, Inc. (ADI).

I am currently looking for new graduate students interested in joining our research group, specifically in the areas of (1) IC design (analog, digital, mixed-signal, and RF), (2) machine learning and artificial intelligence, (3) advanced embedded sensor systems, (4) energy harvesting and storage for sensor nodes, and (5) low-energy long-range and short-range communication systems for sensor nodes. 

Recent Publication/s: 

A. Chua, R. J. Maestro, J. C. Jardin, K. Monisit, R. Nuestro, K.B. Fabay, B. R. Pelayo, W. V. Lofamia, J. R. Ortiz, J. A. Madamba, L. Alarcón, "Smart-Wire: A 0.5V 44uW 0C to 100C power-line energy harvesting sensor node", Proc. 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-3 May 2017. Austin, Texas.

Bacquiran,A., Hizon, J.R., Alarcon, L. (2016). “PVT-aware digital techniques for a power line energy-harvesting sensor node”, Proc. ISCAS 2016, May 22-26, 2016, Montreal, Canada.

Alea, M.D., Hizon, J.R., Alarcon, L. (2016). “Analysis on the error contribution of various leakages to an ultra-low power voltage reference for WSNs”,  Proc. TENSYMP 2016, May 2016.

Alea, M.D., Alarcon, L., Hizon, J.R. (2016), “A modified class of Seok ultra-low power voltage references for wireless sensor nodes,” Proc. TENCON 2015 – 2015 IEEE Region 10 Conference , vol., no., pp.1-4, 1-4 Nov. 2015, Macau.

Panes, A.M., Cabanlong, J.F., Inocencio, D.C., Lodronio, C.L., Hizon, J.R., Alarcon, L. (2015).  “An energy efficient 2.4GHz OOK RF transceiver implemented in a 65nm CMOS process,” Proc. TENCON 2015 – 2015 IEEE Region 10 Conference , vol., no., pp.1-6, 1-4 Nov. 2015, Macau.

Legaspi, P.A., Khan, K., Santiago, K., Sayson, D., Aquino, H., Densing, C.V., Hizon, J.R., Alarcon, L. “Porting an operating system on an ARM-based sensor platform,” Proc. TENCON 2015 – 2015 IEEE Region 10 Conference , vol., no., pp.1-3, 1-4 Nov. 2015, Macau.

Chua, A.N.,  Maestro, R.J.M., Alba, M.E.V , Lofamia, W.V.V., Fabay, K.B., Jardin, J.C., Jocson, K.J., Pelayo, B.R., Madamba, J.A.R., Hizon, J.R., and Alarcón, L. “Delay variation compensation through error correction using RAZOR,” Proc. 6th International Workshop on CMOS Variability (VARI 2015). 1-4 September 2015, Bahia, Brazil.

Luna, A.L., Hizon, J.R., and Alarcon, L. “Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices“, Proc. APCCAS 2014 – IEEE Asia Pacific Conference on Circuits and Systems, Nov 17-20, 2014, Ishigaki Island, Japan.

Barot, F. Jr., Bautista, M.F., Ho, H.H., Misagal, C.C., Peje, J.L., Hizon, J.R., Alarcon, L. “An ultra low-voltage standard cell library in 65-nm CMOS process technology“, Proc. TENCON 2014 – IEEE Region 10 Conference, Oct 22-27, 2014, Bangkok, Thailand.

Magpantay, P., Paprotny, I., Send, R., Xu, Q., Sherman, C., Alarcon, L., White, R., and Wright, “Energy monitoring in smart buildings using wireless sensor networks“, Proc. SMART 2014: The Third International Conference on Smart Systems, Devices and Technologies, Jul 20-24, 2014, Paris, France.

Dela Cruz, Sherlyn, Roque, C.R., Alarcon, L. “1.2V 5.8GHz 90nm CMOS RF Power Amplifier Parameter Enhancement Techniques“, Proc. TENSYMP 2014 – IEEE Region 10 Technical Symposium 2014, Apr 14-16, 2014, Kuala Lumpur, Malaysia.

Alea, M.D., Azurin, L.A., Bamba, P.V., Maramba, M., Santos, E., Alarcon, L., Hizon, J.R., Roque, C.R, “Developing an ARM-based Sensor Platform“, Proc. TENCON 2013 – 2013 IEEE Region 10 Conference, Oct 22-25, 2013, Xi’an, China.

Abadies, H.,  Alvarez, A., Madamba, J.A., Alarcon, L. “The effects of integrated controller techniques on the flash memories“, Proc. International SoC Design Conference (ISOCC) 2013, Nov. 17-18, 2013, Busan, South Korea.

Chua, A., Luna,  A.L., Roque, C.R., Alarcon, L., Oppus, C. Yap, R., Zafra, E.A., Lambino, M., Garcia, R., Hizon, J.R. “Driving Philippine microelectronics education development with multi-university collaboration,” Proc. 2013 IEEE International Conference on Microelectronic Systems Education (MSE), vol., no., pp.52,55, 2-3 June 2013.

Maestro, R. J. M.,  Aquino, H. R. O., Alarcon, L. P. Hizon, J. R. E. “Improving an undergraduate laboratory course for semiconductor device theory to enhance an IC design program,” Proc. 2013 IEEE International Conference on Microelectronic Systems Education (MSE), vol., no., pp.60,63, 2-3 June 2013.

Cabebe, M.J., Gallego, C., Hizon, J.R., Alarcon, L. “Design tradeoffs of 0.5V folded cascode OTA in 65nm CMOS process“, Proceeding of the IEEE Tencon Spring 2013 Conference, 17-19 April 2013, Sydney, Australia.

Maestro, R.J.M., Aquino, H.R.O., Alarcon, L.P., Hizon, J.R.E., “Using a custom designed IC for teaching undergraduate semiconductor device theory,” Proceedings of 5th AUN/SEED-Net Regional Conference in Electrical and Electronics Engineering, 4-5 Feb. 2013.

Alba, M.E.V., Chua, A.N., Lofamia, W.V.V., Maestro,  R.J.M., Hizon, J.R.E., Madamba, J.A.R., Aquino, H.R.O., Alarcon, L.P. “An aggressive power optimization of the ARM9-based core using RAZOR,” Proc. TENCON 2012 – 2012 IEEE Region 10 Conference , vol., no., pp.1,5, 19-22 Nov. 2012.

Fabay, K.B.F., Jardin, J.C.F., Jocson, K.J.C., Pelayo, B.R.D., Alvarez, A.B., Madamba, J.A.R., Alarcon, L.P. “A test port for interfacing and debugging ARM9 processors implemented in FPGA,” Proc. TENCON 2012 – 2012 IEEE Region 10 Conference , vol., no., pp.1,5, 19-22 Nov. 2012.

De Guzman, C.L.S., Nuestro, R.C., Roque, C.K., Alarcon, L.P. “Switched-capacitor converter with low dropout voltage regulator for wireless sensor nodes,” Proc. TENCON 2012 – 2012 IEEE Region 10 Conference , vol., no., pp.1,6, 19-22 Nov. 2012.

Amistoso, R.M.F., Bautista, M.J.A., Delos Santos, R.K.D.P., Ortiz, J.R.R., Alarcon, L.P.,  Ballesil-Alvarez, A., Hizon, J. R. E.“1V supply 16-bit second order sigma-delta modulator in a 90nm CMOS process,” Proc. TENCON 2012 – 2012 IEEE Region 10 Conference , vol., no., pp.1,4, 19-22 Nov. 2012

Domingo, M.E., Ostia, F. Reas, R., Alarcon, L., Alvarez, A. “Comparative study of low-leakage SRAM structures using 90nm CMOS technology”. Proceedings of the IEEE Region 10 Conference 2010 (TENCON2010). Fukuoka, Japan. November 21-24, 2010.

Abaya, T., Ancajas, D.M., Ballesil-Alvarez, A., Alarcon, L. “0.6V correlators for WLAN receivers”, Proceedings of the IEEE Sarnoff Symposium, New Jersey, USA. March 30 – April 1, 2009.

Almazan, S., Zarsuela, J.V., Ballesil, A.P., Alarcon, L.P. “A Study on the effect of varying voltage supply on the performance of voltage sense amplifiers for 1-Transistor DRAM memories,” Proc. 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008). , vol., no., pp.108-112, 25-27 Nov. 2008.

Lorenzo, M.A.G., Tan, W.M., Ballesil, A.P., Alarcon, L.P. “Experimental analysis of read related transistors’ gate width sizing effects on the 3T1D DRAM access time curve,” Proc 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), vol., no., pp.450-454, 25-27 Nov. 2008.

Gusad, M.T., Alarcon, L.P. “Comparison of CMOS LNAs implemented with different capacitor and inductor structures,” Proc. 2006 Asia-Pacific Microwave Conference (APMC 2006), vol., no., pp.397-400, 12-15 Dec. 2006.

Gusad, M.T.A., Alarcon, L.P. “A study on the effects of the structure of passive devices on the performance of CMOS low-noise amplifiers,” Proc. 2006 IEEE Region 10 Conference (TENCON 2006), vol., no., pp.1-4, 14-17 Nov. 2006.

Hizon, J.R.E., Rosales, M.D., Tan, H.L.B., Alarcon, L.P. , Sabido, D.J. “RF passives for a 0.25 μm digital CMOS process,” Proc. 2006 Asia-Pacific Microwave Conference (APMC 2006), vol., no., pp.1333-1336, 12-15 Dec. 2006.

Mangaser, J.E.R., Gutierrez, M.C.N., Hizon,J.R.E.  Alarcon, L.P. “A study on RF transistor implementations on a 0.25 μm digital CMOS process,” Proc. 2006 IEEE Region 10 Conference (TENCON 2006), vol., no., pp.1-4, 14-17 Nov. 2006.

Hizon, J.R.E., Rosales, M.D., Alarcon, L.P., Sabido, D.J. “Integrating spiral inductors on 0.25 μm epitaxial CMOS process,” Proc. 2005 Asia-Pacific Conference Microwave Conference Proceedings, (APMC Proceedings) , vol.1, no., pp. 4 pp., 4-7 Dec. 2005.

Gusad,M.T.A., Alarcon, L.P.  “Design methodology for CMOS low-noise amplifiers using power matching techniques,” Proc. 2005 IEEE Region 10 Conference (TENCON 2005), vol., no., pp.1-5, 21-24 Nov. 2005.

Rosales, M.D., Hizon, J.R.E., Alarcon, L.P., Sabido, D.J. “Monolithic spiral Inductors for a 0.25 μm digital CMOS process,” Proc . 2005 IEEE Region 10 Conference (TENCON 2005), vol., no., pp.1-6, 21-24 Nov. 2005.

Hizon, J.R.E., Rosales, M.D., Alarcon, L.P., Sabido, D.J. “Spiral Inductor Coupling on 0.25 μm Epitaxial CMOS Process,” Proc . 2005 IEEE Region 10 Conference (TENCON 2005), vol., no., pp.1-5, 21-24 Nov. 2005.

Hizon, J.R.E., Rosales, M.D., Alarcon, L.P., Sabido, D.J. IX; , “Characterization of monolithic spiral inductors on a 0.25 μm digital CMOS process,” Proc . 2004 IEEE Region 10 Conference (TENCON 2004), vol.D, no., pp. 360- 363 Vol. 4, 21-24 Nov. 2004.