Electrical and Electronics Engineering Institute

University of the Philippines - Diliman

Joy Alinda Madamba

Position: 
Assistant Professor
Laboratory Affiliation: 
Intel Microprocessors Laboratory
Room: 
409
Telephone Number: 
+63-2-9818500 loc 3383
Educational Background: 
PhD Electrical and Electronics Engineering, University of the Philippines Diliman (on-going)
Recent Publication/s: 

J.A.R. Madamba, and Francis Joseph Seriña, “Efficient load balancing technique for parallel ray tracing using a reservoir,” Journal of Computational Innovations and Engineering Applications, Vol. 1 No. 2, January 2017.

A. Chua, J.A.R., Madamba, et.al., “Smart-Wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor node,” Proceedings of the 2017 IEEE Custom Integrated Circuits Conference (CICC), USA.

A. Chua, J.A.R., Madamba, et.al., “Delay variation compensation through error correction using RAZOR,” Proceedings of the 6th International Workshop on CMOS Variability. Brazil, 2015.

J. A. R. Madamba, L. Alarcon, “Cost and effect of applying redundancy to improve the resiliency of a wireless sensor network (WSN),” Proceedings of the 8th AUN/SEED-Net Regional Conference on Electrical and Electronics Engineering. Philippines, 2015.

H. Abadies, L. P. Alarcon, J.A.R. Madamba, et.al., “5.8 GHz integer-n phase-locked loop frequency synthesizer for WiMax receivers in 65nm CMOS,” Proc. Analog Devices Technical Symposium. Philippines, 2013.

L.P. Alarcon, M.E. Alba, J.A.R. Madamba,  et.al., “Verification of Razorized ARM9 core through ARM9TDM co-processing,” Analog Devices Technical Symposium, Philippines, 2013.

H. Abadies, J. A. R. Madamba, et.al., “The effects of integrated controller techniques on the performance of flash memories,” Proceedings of the International SoC Design Conference. Korea, 2013.

H. Abadies, J.A.R. Madamba, et.al., “A fast parallel RS decoder in 65nm technology”. Proceedings of the 8th ERDT Conference. Philippines.

M. E. Alba, J. A. R. Madamba, et.al., “An aggressive power-optimization of the ARM9-based core using RAZOR,” Proceedings of the IEEE Region 10 Conference (TENCON). Philippines, 2012.

K.B. Fabay, J. A. R. Madamba, et.al., “A test port for interfacing and debugging ARM9 processors implemented in FPGA,” Proceedings of the IEEE Region 10 Conference (TENCON). Philippines, 2012.

F.J. Seriña, J.A.R. Madamba, “Reservoir: an alternative load balancing technique for parallel ray tracing,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation. Philippines, 2011.

A.J.M. ,Difontorum,  J.A.R Madamba, et.al., “A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA,” Proceedings of the IEEE Region 10 Conference (TENCON). Indonesia, 2011..

N.J. Barahan,  J.A.R. Madamba, et.al., “SCARM: A memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor,” Proceedings of the IEEE Region 10 Conference (TENCON). Indonesia, 2011.

S.J.A.V. Sebastian, , J.A.R. Madamba, et.al., “Implementation of the Phase II compiler for the ARM7TDMI-S dual-core microprocessor,” Proceedings of the 2nd International Conference on Intelligent Systems, Modeling and Simulation (ISMS). Cambodia, 2011.

J.B.A Constantino, J.A.R. Madamba, 2011. “Dual edge flip flop implementations of the 90nm process,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation, Philippines, 2011.

J.B.A Constantino, J.A.R. Madamba, “Logic style comparison using 32-Bit CLA in 90nm technology,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation, Philippines, 2011.

A.J.J. Tang, J.A.R. Madamba, “Comparative analysis of low power multiplier architectures,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation, Philippines, 2011.

C.D.C.Arandilla, J.A.R., Madamba, “Comparison of replica bitline technique and chain delay technique as read timing control for low power asynchronous SRAM,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation, Philippines, 2011.

F.J., Seriña, J.A.R. Madamba, “Reservoir: an alternative load balancing technique for parallel ray tracing,” Proceedings of the 5th Asia International Conference on Mathematical Modeling and Computer Simulation. Philippines, 2011

A., Buenaventura, J.A.P Reyes, et.al., “Power optimized partial scan BIST implementation on DLX microprocessor,” Proceedings of the 2010 International Conference on System-on-Chip Design Challenges. Philippines, 2010.

J. Abatayo, J., J.A.P.Reyes, et.al., “Design and implementation of ARM7 microprocessor with single-precision floating-point coprocessor,” Proceedings of the 2010 International Conference on System-on-Chip Design Challenges. Philippines, 2010.

C.Arandilla, J.A.P. Reyes, et.al., “High level implementation of the five stage pipelined ARM9TDM core,” Proceedings of the IEEE Region 10 Conference (TENCON). Japan, 2010.

R. Reas , A Alvarez, J.A.,P. Reyes, ''Simulation of standard benchmarks in hardware implementations of L2 cache models in Verilog HDL,” Proceeding of the UKSim- IEEE 12th International Conference on Computer Modelling and Simulation, England, 2010.

J. Zarsuela, A. Alvarez, J.A.,P. Reyes,  ''A simulation of cache sub-banking and block buffering as power reduction techniques for multiprocessor cache design,'' Proceedings of the UKSim-IEEE 12th International Conference on Computer Modelling and Simulation. England, 2010.

P. Bautista, J.A.P., Reyes,et.al., ''Project GRAMS and DLXPlus: visual tools for computer architecture and organization education''. Proceedings of the International Technology, Education, and Development Conference, Spain, 2009.

A.L., Luna, J.A.P., Reyes, et.al., ''Implementation of the complete ARM7TDMI-S instruction set on a debug capable core,'' Proceedings of the 2009 National Electrical, Electronics and Computing Conference. Philippines.

C. Dumaguing, J.A.P Reyes, et.al., ''An asynchronous implementation of a 32-bit DLX microprocessor''. Proceedings of the 2009 International Conference on Information and Multimedia Technology, South Korea, 2009.

J. Jayme, J.,A.P  Reyes, et.al. ''Analysis of different AMBA-based bus interconnection schemes for ARM7 multicore environment.'' Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), USA, 2008.

D Dioquino, J.A.P.Reyes, et.al., ''Design and implementation of a 32-bit dual core capable DLX microprocessor with single-level cache,'' Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, 2008.

P. Bautista, P., J.A.P. Reyes, et.al., ''Project GRAMS: a graphical reconfigurable architecture MIPS simulator''. Proceedings of the IEEE Region 10 Conference, India, 2008.

D.M.B Ancajas, J.A.P. Reyes, et.al., ''Dual core capability of a 32-bit DLX microprocessor''. Proceedings of the IEEE Region 10 Conference, Taiwan, 2007.

N. Azucena, J.A.P.  Reyes,, et.al., ''High-level implementation of an ARM7 microprocessor with multicore capabilities,'' Proceedings of the IEEE Region 10 Conference. Taiwan, 2007.

J.E.H., Aguilar, J.A.P Reyes, et.al., ''DLX Gold: design and implementation of a DLX microprocessor with single precision floating- point operations,'' Proceedings of the IEEE Region 10 Conference, Taiwan, 2007.

A. Ostrea, J.A.P Reyes, et.al., ''C Compiler back end for the dual core capable DLX microprocessor,'' Proceedings of the 8th National ECCE Conference. Philippines, 2007.

D. A.Dioquino,  J. A. P. Reyes, et.al., ''Design and implementation of a 32-bit dual core capable DLX microprocessor with single-level cache,''Proceedings of the 8th National ECCE Conference. Philippines, 2007.

 J.A.C., Bautista, J.A.P.Reyes, et. al., ''High-level design implementation and characterization of a 32-Bit 5-stage pipelined DLX microprocessor with single level cache,'' Proceedings of the 2nd International Engineering Research Conference. Philippines, 2006.

J.A.P.Reyes, L P. Alarcon,  et. al., ''A study of floating-point architectures for pipelined RISC processors,'' Proceedings of the IEEE International Symposium on Circuits and Systems. Greece, 2006.

D.F. Cantavieja,  J.A.P.Reyes, ''Design and implementation of a power-optimized DLX microprocessor,'' Proceedings of the 6th National Electronics and Communications Engineering Conference (ECECONF 2005), Philippines, 2005.